1. Field
This disclosure relates generally to semiconductor device design, and more specifically, to tracking cumulative process-induced damage to semiconductor device gate dielectrics during routing of interconnect layers.
2. Related Art
Integrated circuit devices are typically formed as a set of layers deposited or grown on a substrate. Transistor devices in integrated circuits have a conductive gate formed over a channel region of the transistor. The conductive gate is separated from the channel region by a gate dielectric. Conductive interconnect layers can be formed in electrical contact with the conductive gate.
During the process of forming the conductive interconnect layers, each conductive interconnect layer can be exposed to deposition and etching processes. During plasma etching and plasma deposition processes, electric charges can collect on exposed conductive layers. These electric charges can, through the electrical interconnect, form a potential difference between the conductive gate of a transistor and the underlying channel region through the gate dielectric. If the collected charge is large enough, the potential difference increases beyond the normal operating voltage of the integrated circuit device, and the gate dielectric can break down. This process-induced damage can occur for both silicon dioxide dielectrics and high-k dielectric materials. In practice, process-induced damage can be more of an issue for high-k dielectric materials because those dielectric materials by their nature do not leak current and therefore do not reduce collected charge as readily as silicon dioxide materials.
The relationship between the exposed area of each conductive layer during processing, the processes to which each conductive layer is exposed, and the area of the conductive gate determines the collected charge, and each device has a limit of charge that can be collected before the device may get damaged. This limit is called an antenna rule. Typical antenna rules look at each conductive layer individually or in small groups. These antenna rules are taken into consideration during a routing design of the integrated circuit. If an antenna rule is violated for a particular layer or group of layers, the design fails the antenna rule and the connections must be reevaluated.
Typical antenna rules do not take into account design choices that provide interconnect layers that are significantly under an antenna rule ratio, and which may permit a more aggressive approach for conductive interconnect area of a later formed interconnect layer.
It is therefore desirable to implement rules that provide a more flexible implementation of process-induced damage that can take into account historical performance under antenna rules, as well as mechanisms for automatically resolving antenna rule violation warnings or process-induced damage due to antenna rule violations.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.